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| rev. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: ? analog devices, inc. all rights reserved. adn8830 thermoelectric cooler controller features high efficiency small size: 5 mm 5 mm lfcsp low noise: <0.5% tec current ripple long-term temperature stability: 0.01 c temperature lock indication temperature monitoring output oscillator synchronization with an external signal clock phase adjustment for multiple controllers programmable switching frequency up to 1 mhz thermistor failure alarm maximum tec voltage programmability applications thermoelectric cooler (tec) temperature control resistive heating element control temperature stabilization substrate (tss) control functional block diagram pid compensation network temperature measurement amplifier pwm controller from thermistor temperature set input vo ltag e reference v ref oscillator frequency/phase control p-channel (upper mosfet) n-channel mosfet drivers p-channel (lower mosfet) n-channel general description the adn8830 is a monolithic controller that drives a thermo- electric cooler (tec) to stabilize the temperature of a laser diode or a passive component used in telecommunications equipment. this device relies on a negative temperature coefficient (ntc) thermistor to sense the temperature of the object attached to the tec. the target temperature is set with an analog input voltage either from a dac or an external resistor divider. the loop is stabilized by a pid compensation amplifier with high stability and low noise. the compensation network can be adjusted by the user to optimize temperature settling time. the component values for this network can be calculated based on the thermal transfer function of the laser diode or obtained from the lookup table given in the application notes section. voltage outputs are provided to monitor both the temperature of the object and the voltage across the tec. a voltage reference of 2.5 v is also provided. 2012 d 781/461-3113
rev. C2C adn8830Cspecifications (@ v dd = 3.3 v to 5.0 v, v gnd = 0 v, t a = 25 c, t set = 25 c, using typical application configuration as shown in figure 1, unless otherwise noted.) parameter symbol conditions min typ max unit temperature stability long-term stability using 10 k thermistor with = C4.4% at 25 c 0.01 c pwm output drivers output transition time t r , t f c l = 3,300 pf 20 ns nonoverlapping clock delay 50 65 ns output resistance r o (n1, p1) i l = 50 ma 6 output voltage swing out a v lim = 0 v 0 v dd v output voltage ripple out a f clk = 1 mhz 0.2 % output current ripple i tec f clk = 1 mhz 0.2 % linear output amplifier output resistance r o, p2 i out = 2 ma 85 r o, n2 i out = 2 ma 178 output voltage swing out b 0 v dd v power supply power supply voltage v dd 3.0 5.5 v power supply rejection ratio psrr v dd = 3.3 v to 5 v, v tec = 0 v 80 92 db C40 c t a +85 c60 db supply current i sy pwm not switching 8 12 ma C40 c t a +85 c15ma shutdown current i sd pin 10 = 0 v 5 a soft-start charging current i ss 15 a undervoltage lockout v olock low-to-high threshold 2.0 2.7 v error amplifier input offset voltage v os v cm = 1.5 v 50 250 v gain a v, in 20 v/v input voltage range v cm 0.2 2.0 v common-mode rejection ratio cmrr 0.2 v < v cm < 2.0 v 58 68 db C40 c t a +85 c55 db open-loop input impedance r in 1g gain-bandwidth product gbw 2 mhz reference voltage reference voltage v ref i ref < 2 ma 2.37 2.47 2.57 v oscillator synchronization range f clk pin 25 connected to external clock 200 1,000 khz oscillator frequency f clk pin 24 = v dd ; (r = 150 k ; 800 1,000 1,250 khz pin 25 = gnd) logic control * logic low input threshold 0.2 v logic high input threshold 3 v logic low output level 0.2 v logic high output threshold v dd C 0.2 v * logic inputs meet typical cmos i/o conditions for source/sink current (~1 a). specifications subject to change without notice. d rev. adn8830 C3C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adn8830 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings * supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v input voltage . . . . . . . . . . . . . . . . . . . . . . . gnd to v s + 0.3 v storage temperature range . . . . . . . . . . . . . C65 c to +150 c operating temperature range . . . . . . . . . . . . C40 c to +85 c operating junction temperature . . . . . . . . . . . . . . . . . . 125 c lead temperature range (soldering, 10 sec) . . . . . . . . 300 c esd ratings 883 (human body) model . . . . . . . . . . . . . . . . . . . . . . 1.0 kv * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin configuration pin 1 indicator top view 24 composc 23 pgnd 22 n1 21 p1 thermfault 1 thermin 2 sd 3 32 nc 20 pvdd 19 out a 18 compswin 17 compswout out b 9 n2 10 p2 11 tempctl 12 compfb 13 compout 14 vlim 15 vtec 16 tempset 4 templock 5 nc 6 vref 7 avdd 8 31 tempout 30 agnd 29 phase 28 syncout 27 softstart 26 freq 25 syncin adn8830 nc = no connect package type ja * jc unit 32-lead lfcsp (acp) 35 10 c/w * ja is specified for worst-case conditions, i.e., ja is specified for a device soldered in a 4-layer circuit board for surface-mount packages. d the exposed pad on the bottom of the package must be connected to v cc or the gnd plane. rev. C4C adn8830 pin function descriptions pin no. mnemonic type description 1 thermfault digital output indicates an open or short-circuit condition from thermistor. 2 thermin analog input thermistor feedback input. 3 sd digital input puts device into low current shutdown mode. active low. 4 tempset analog input target temperature input. 5 templock digital output indicates when thermistor temperature is within 0.1 c of target tem- perature as set by tempset voltage. 6 nc no connection, except as noted in the application notes section. 7 vref analog output 2.5 v reference voltage. 8 avdd power power for nondriver sections. 3.0 v min; 5.5 v max. 9 out b analog input linear output feedback. will typically connect to tec+ pin of tec. 10 n2 analog output drives linear output external nmos gate. 11 p2 analog output drives linear output external pmos gate. 12 tempctl analog output output of error amplifier. connects to compfb through feedforward section of compensation network. 13 compfb analog input feedback summing node of compensation amplifier. connects to tempctl and compout through compensation network. 14 compout analog output output of compensation amplifier. connects to compfb through feed- back section of compensation network. 15 vlim analog input sets maximum voltage across tec. 16 vtec analog output indicates relative voltage across the tec. the 1.5 v corresponds to 0 v across tec. the 3.0 v indicates maximum output voltage, maximum heat transfer through tec. 17 compswout analog output compensation for switching amplifier. 18 compswin analog input compensation for switching amplifier. capacitor connected between compswin and compswout. 19 out a analog input pwm output feedback. will typically connect to tecC pin of tec. 20 pvdd power power for output driver sections. 3.0 v min; 5.5 v max. 21 p1 digital output drives pwm output external pmos gate. 22 n1 digital output drives pwm output external nmos gate. 23 pgnd ground power ground. external nmos devices connect to pgnd. can be connected to digital ground as noise sensitivity at this node is not critical. 24 composc analog input connect as indicated in the application notes section. 25 syncin digital input optional clock input. if not connected, clock frequency set by freq pin. 26 freq analog input sets switching frequency. 27 softstart analog input controls initialization time for adn8830 with capacitor to ground. 28 syncout digital output phase adjusted clock output. phase set from phase pin. can be used to drive syncin of other adn8830 devices. 29 phase analog input sets switching and syncout clock phase relative to syncin clock. 30 agnd ground analog ground. should be low noise for highest accuracy. 31 tempout analog output indication of thermistor temperature. 32 nc no connection. d ep exposed pad the exposed pad on the bottom of the package must be connected to v cc or the gnd plane. rev. typical performance characteristicsCadn8830 C5C time (20ns/div) 0 00 0 voltage (1v/div) 00000000 p1 n1 v dd = 5v t a = 25 c tpc 1. n1 and p1 rise time time (20ns/div) 0 00 0 voltage (1v/div) 00000000 v dd = 5v t a = 25 c p1 n1 tpc 2. n1 and p1 fall time 360 320 0 phase shift (degrees) 160 120 80 40 240 200 280 vphase (v) 2.4 0.4 0.8 1.2 1.6 2.0 0 sync in = 1mhz t a = 25 c tpc 3. clock phase shift vs. phase voltage 320 0 phase shift (degrees) 160 120 80 40 240 200 280 vphase (v) 2.4 0.4 0.8 1.2 1.6 2.0 0 sync in = 200khz t a = 25 c 360 tpc 4. clock phase shift vs. phase voltage temperature ( c) 2.480 2.475 2.455 C40 85 C15 v ref ( v) 10 35 60 2.470 2.465 2.460 tpc 5. v ref vs. temperature r freq (k ) 1,000 800 0 0 1,500 250 500 750 1,000 1,250 600 400 200 v dd = 5v t a = 25 c switching frequency (khz) tpc 6. switching frequency vs. r freq d rev. C6C adn8830 temperature ( c) 1,000 920 C40 85 C15 switching frequency (khz) 10 35 60 980 960 940 930 990 970 950 v dd = 5v r freq = 150k tpc 7. switching frequency vs. temperature temperature ( c) 70 30 C40 85 C15 offset voltage ( v) 10 35 60 55 45 35 65 60 50 40 tpc 8. offset voltage vs. temperature common-mode voltage (v) 200 C100 C400 0 2.0 0.2 offset voltage ( v) 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 100 0 C200 C300 tpc 9. offset voltage vs. common-mode voltage switching frequency (khz) 200 1,000 300 400 500 600 700 800 900 45 40 0 supply current (ma) 20 15 10 5 30 25 35 v dd = 5v t a = 25 c using circuit shown in figure 1 tpc 10. supply current vs. switching frequency temperature ( c) 2.06 2.02 C40 85 C15 therm fault upper threshold (v) 10 35 60 2.04 2.03 2.05 tpc 11. open thermistor fault threshold vs. temperature temperature ( c) 0.26 0.23 C40 85 C15 therm fault lower threshold (v) 10 35 60 0.25 0.24 tpc 12. short thermistor fault threshold vs. temperature d rev. adn8830 C7C application notes principle of operation the adn8830 is a controller for a tec and is used to set and stabilize the temperature of the tec. a voltage applied to the input of the adn8830 corresponds to a target temperature setpoint. the appropriate current is then applied to the tec to pump heat either to or away from the object whose tem- perature is being regulated. the temperature of the object is measured by a thermistor and is fed back to the adn8830 to correct the loop and settle the tec to the appro priate final temperature. for best stability, the thermistor should be mounted in close proximity to the object. in most laser diode modules, the tec and thermistor are already mounted in the unit and are used to regulate the temperature of the laser diode. a complete tec controller solution requires: ? a precision input amplifier stage to accurately measure the difference between the target and object temperatures. ? a compensation amplifier to optimize the stability and temperature settling time. ? a high output current stage. because of the high output currents involved, a tec controller should operate with high efficiency to minimize the heat generated from power dissipation. in addition, an effective controller should operate down to 3.3 v and have an indication of when the target temperature has been reached. the adn8830 accomplishes all of these requirements with a minimum of external components. figure 1 shows a reference design for a typical application. temperature is monitored by connecting the measurement thermistor to a precision amplifier, called the error amplifier, with a simple resistor divider. this voltage is compared against the temperature set input voltage, creating an error voltage that is proportional to their difference. to maintain accurate wave- length and power from the laser diode, this difference voltage must be as accurate as possible. for this reason, self-correction auto-zero amplifiers are used in the input stage of the adn8830, providing a maximum offset voltage of 250 v over time and temperature. this results in final temperature accuracy within 0.01 c in typical applications, eliminating the adn8830 as an error source in the temperature control loop. a logic output is provided at templock to indicate when the target tem perature has been reached. the output of the error amplifier is then fed into a compensa- tion amplifier. an external network consisting of a few resistors and capacitors is connected around the compensation amplifier. this network can be adjusted by the user to optimize the step thermfault thermin rth 10k @25 c r2 7.68k 0.1% vref c8 10 f 3.3v vref templock tempset r3 10k 0.1% r4 7.68k 0.1% vtec 9 10 11 12 13 14 15 16 c9 10 f r6 100k r5 205k c11 1 f r7 1m 24 23 22 21 20 19 18 17 3.3v adn8830 c5 10nf 3.3v tec+ c7 10 f q3 fdw2520c-a q4 fdw2520c-b c4 22 f cde esrd 3.3v q2 fdw2520c-a tecC c3 10 f l1 4.7 h coilcraft do3316-472 q1 fdw2520c-b 32 31 30 29 28 27 26 25 c1 0.1 f r1 150k syncout tempout 3.3v c6 2.2nf c10 330pf 3.3v c12 3.3nf c2 22 f cde esrd 1 2 3 4 5 6 7 8 figure 1. typical application schematic d rev. C8C adn8830 response of the tecs temperature either in terms of settling time or maximum current change. details of how to adjust the compen- sation network are given in the compensation loop section. the adn8830 can be easily integrated with a wavelength locker for fine-tune temperature adjustment of the laser diode for a specific wavelength. this is a useful topology for tunable wave- length lasers. details are highlighted in the using the tec controller adn8830 with a wave locker section. the tec is driven differentially using an h-bridge configura- tion to maximize the output voltage swing. the adn8830 drives external transistors that are used to provide current to the tec. these transistors can be selected by the user based on the maximum output current required for the tec. the maximum voltage across the tec can be set through use of the vlim pin on the adn8830. to further improve the power efficiency of the system, one side of the h-bridge uses a switched output. only one inductor and one capacitor are required to filter out the switching frequency. the output voltage ripple is a function of the output inductor and capacitor and the switching frequency. for most applica- tions, a 4.7 h inductor, 22 f capacitor, and switching frequency of 1 mhz maintains less than 0.5% worst-case output voltage ripple across the tec. the other side of the h-bridge does not require any additional circuitry. the oscillator section of the adn8830 controls the switched output section. a single resistor sets the switching frequency from 100 khz to 1 mhz. the clock output is available at the syncout pin and can be used to drive another adn8830 device by connecting to its syncin pin. the phase of the clock is adjusted by a voltage applied to the phase pin, which can be set by a simple resistor divider. phase adjustment allows two or more adn8830 devices to operate from the same clock frequency and not have all outputs switch simultaneously, which could create an excessive power supply ripple. details of how to adjust the clock frequency and phase are given in the setting the switching frequency section. for effective indication of a catastrophic system failure, the adn8830 alerts to open-circuit or short-circuit conditions from the thermistor, preventing an erroneous and potentially damaging temperature correction from occurring. with some additional external circuitry, output overcurrent detection can be imple- mented to provide warning in the event of a tec short-circuit failure. this circuit is highlighted in the setting maximum output current and short-circuit protection section. signal flow diagram figure 2 shows the signal flow diagram through the adn8830. the input amplifier is fixed with a gain of 20. the voltage at tempctl can be expressed as tempctl tempset thermin = () + 20 1 5 C. (1) when the temperature is settled, the thermistor voltage will be equal to the tempset voltage, and the output of the input amplifier will be 1.5 v. the voltage at tempctl is then fed into the compensation amplifier whose frequency response is dictated by the compen- sation network. details on the compensation amplifier can be found in the compensation loop section. when configured as a simple integrator or pid loop, the dc forward gain of the compensation section is equal to the open-loop gain of the compensation amplifier, which is over 80 db or 10,000. the output from the compensation loop at compout is then fed to the linear amplifier. the output of the linear amplifier at out b is fed with compout into the pwm amplifier whose output is out a. these two outputs provide the voltage drive directly to the tec. including the external transistors, the gain of the differential output section is fixed at 4. details on the output amplifiers can be found in the output driver amplifiers section. 1.5v input amplifier a v = 20 compensation amplifier a v = z2/z1 1.5v z1 a v = 4 pwm/linear amplifiers out a out b z2 tempset thermin 4 2 12 13 14 19 9 tempctl compout compfb figure 2. signal flow block diagram of the adn8830 thermistor setup the temperature of the thermal object, such as a laser diode, is detected with a negative temperature coefficient (ntc) thermistor. the thermistors resistance exhibits an exponential relationship to the inverse of temperature, meaning the resistance decreases at higher temperatures. thus, by measuring the thermistor resistance, temperature can be ascertained. betatherm is a leading supplier of ntc thermistors. thermistor information and details can be found at www.betatherm.com. for this application, the resistance is measured using a voltage divider. the thermistor is connected between thermin (pin 2) and agnd (pin 30). another resistor (r x ) is connected be tween vref (pin 7) and thermin (pin 2), creating a voltage divider for the vref voltage. figure 3 shows the schematic for this configuration. v dd adn8830 8 7 2 30 r therm r x figure 3. connecting a thermistor to the adn8830 with the thermistor connected from thermin to agnd, the voltage at thermin will decrease as temperature increases. to maintain the proper input-to-output polarity in this configu- ration, out a (pin 19) should connect to the tecC pin on the tec, and out b (pin 9) should connect to the vtec+ pin. the thermistor can also be connected from vref to thermin with r x connecting to ground. in this case, out a must connect to tec+ with out b connected to tecC for proper operation. d rev. adn8830 C9C although the thermistor has a nonlinear relationship to tem- perature, near optimal linearity over a specified temperature range can be achieved with the proper value of r x . first, the resistance of the thermistor must be known, where rrtt rtt rtt therm t low tmid t high == == == 1 2 3 @ @ @ (2) t low and t high are the endpoints of the temperature range and t mid is the average. these resistances can be found in most thermistor data sheets. in some cases, only the coefficients corresponding to the steinhart-hart equation are given. the steinhart-hart equation is 1 11 3 t abnr cnr =+ () + () [] (3) where t is the absolute temperature of the thermistor in kelvin (k = c + 273.15), and r is the resistance of the thermistor at that temperature. based on the coefficients a , b , and c , r therm can be calculated for a given t , albeit somewhat tediously, by solving the cubic roots of this equation r therm =++ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ++ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? exp C C C ? ? 2427 2427 2 3 1 2 1 3 2 3 1 2 1 3 (4) where x a t c = C 1 and = b c r x is then found as r rr r r rr rr r x tt t t tt tt t = + + 12 23 13 13 2 2 2 C C (5) for the best accuracy as well as the widest selection range for resistances, r x should be 0.1% tolerance. naturally, the smaller the temperature range required for control, the more linear the voltage divider will be with respect to temperature. the voltage at thermin is v vref r rr x therm therm x = + (6) where vref has a typical value of 2.47 v. the adn8830 control loop will adjust the temperature of the tec until v x equals the voltage at tempset (pin 4), which we define as v set . target temperature can be set by vmtt v set mid xmid = () + C (7) where t equals the target temperature, and m vv tt x high x low high low = ,, C C (8) v x for high, mid, and low are found by using equation 6 and substituting r t3 , r t2 , and r t1 , respectively, for r therm . the variable m is the change in v x with respect to temperature and is expressed in v/ c. the setpoint voltage can be driven from a dac or another voltage source, as shown in figure 4. the reference voltage for the dac should be connected to vref (pin 7) on the adn8830 to ensure best accuracy from device to device. for a fixed target temperature, a voltage divider network can be used as shown in figure 5. r1 is set equal to r x , and r2 is equal to the value of r therm at the target temperature. 3.3v adn8830 8 4 7 30 ad7390 6 8 5 3.3v 7 1C4 c figure 4. using a dac to control the temperature setpoint 3.3v adn8830 8 7 4 30 r2 r1 figure 5. using a voltage divider to set a fixed temperature setpoint design example 1 a laser module requires a constant temperature of 25 c. from the manufacturers data sheet, we find the thermistor in the laser module has a value of 10 k at 25 c. because the laser is not required to operate at a range of temperatures, the value of r x can be set to 10 k . tempset can be set by a simple resistor divider as shown in figure 5, with r1 and r2 both equal to 10 k . design example 2 a laser module requires a continuous temperature control from 5 c to 45 c. the manufacturers data sheet shows the therm istor has a value of 10 k at 25 c, 25.4 k at 5 c, and 4.37 k at 45 c. using equation 5, r x is calculated to be 7.68 k to yield the most linear temperature-to-voltage conversion. a dac will be used to set the tempset voltage. dac resolution for tempset the temperature setpoint voltage to thermin can be set from a dac. the dac must have a sufficient number of bits to achieve adequate temperature resolution from the system. the voltage range for thermin is found by multiplying the variable m from equation 8 by the temperature range. thermin voltage range m t t max min = () C (9) from design example 2, 40 c of the control temperature range is achieved with a voltage range of only 1 v. d rev. C10C adn8830 to eliminate the resolution of the dac as the principal source of system error, the step size of each bit, v step , should be lower than the desired system resolution. a practical value for absolute dac resolution is the equivalent of 0.05 c. the value of v step should be less than the value of m from equation 8 multiplied by the desired temperature resolution, or vcm step < 005 . (10) where m is the slope of the voltage-to-temperature conversion line, as found from equation 8. from design example 2, where m = 25 mv/ c, we see the dac should have resolution better than 1.25 mv per step. the minimum number of bits required is then given as number of bits vv fs step = () ( ) () log C log log 2 (11) where v fs is the full-scale output voltage from the dac, which should be equal to the reference voltage from the adn8830, vref = 2.47 v as given in the specifications table for the refer ence voltage. in this example, the minimum resolution is 11 bits. a 12-bit dac, such as the ad7390, can be readily found. it is important that the full-scale voltage input to the dac is tied to the adn8830 reference voltage, as shown in figure 4. this eliminates errors from slight variances of vref. thermistor fault and temperature lock indications both the thermfault (pin 1) and templock (pin 5) outputs are cmos compatible outputs that are active high. thermfault will be a logic low while the thermistor is operating normally and will go to a logic high if a short or open is detected at thermin (pin 2). the trip voltage for thermfault is when thermin falls below 0.2 v or exceeds 2.0 v. thermfault provides only an indication of a fault condition and does not activate any shutdown or protec- tion circuitry on the adn8830. to shut down the adn8830, a logic low voltage must be asserted on pin 3, as described in the shutdown mode section. templock will output a logic high when the voltage at thermin is within 2.5 mv of tempset. this voltage can be related to temperature by solving for m from equation 8. for most laser diode applications, 2.5 mv is equivalent to 0.1 c. if the voltage difference between thermin and tempset is greater than 2.5 mv, then templock will output a logic low. the input offset voltage of the adn8830 is guaranteed to w ithin 250 v, which for most applications is within 0.01 c. setting the switching frequency the adn8830 has an internal oscillator to generate the switch- ing frequency for the output stage. this oscillator can be either set in free-run mode or synchronized to an external clock signal. for free-run operation, syncin (pin 25) should be connected to ground and composc (pin 24) should be connected to avdd. the switching frequency is then set by a single resistor connected from freq (pin 26) to ground. table i shows r freq for some common switching frequencies. table i. switching frequencies vs. r freq f switch r freq 100 khz 1.5 m 250 khz 600 k 500 khz 300 k 750 khz 200 k 1 mhz 150 k for other frequencies, the value for this resistor, r freq , should be set to r f freq switch = 150 10 9 (12) where f switch is the switching frequency in hz. higher switching frequencies reduce the voltage ripple across the tec. however, high switch frequencies will create more power dissipation in the external transistors. this is due to the more frequent charging and discharging of the transistors gate capacitances. if large transistors are needed for a high output current application, faster switching frequencies could reduce the overall power efficiency of the circuit. this is covered in detail in the calculating power dissipation and efficiency section. the switching frequency of the adn8830 can be synchronized with an external clock by connecting the clock signal to syncin (pin 25). pin 24 should also be connected to an r-c net work, as shown in figure 6. this network is simply used to compen sate a pll to lock on to the external clock. to ensure the quickest synchronization lock-in time, r freq should be set to 1.5 m . adn8830 freq composc 1.5m 26 24 0.1 f 1k 1nf figure 6. using an r-c network on pin 24 with an external clock the relative phase of the adn8830 internal oscillator compared to the external clock signal can be adjusted. this is accomplished by adjusting the voltage to phase (pin 29) according to tpcs 3 and 4. the phase shift versus voltage can be approximated as phase shift v vref phase = 360 (13) where v phase is the voltage at pin 29, and vref has a typical value of 2.47 v. to ensure the oscillator operates correctly, v phase should remain higher than 100 mv and lower than 2.3 v. this is required for either internal clock or external sync hronization operation. a resistor di vider from vref to ground can establish this voltage easily, although any voltage source, such as a dac, could be used as well. if phase is not a consideration, for example with a single adn8830 being used, pin 29 can be tied to pin 6, which pro- vides a 1.5 v reference voltage. d rev. adn8830 C11C the phase adjusted output from the adn8830 is available at syncout (pin 28). this pin can be used as a master clock signal for driving other adn8830 devices. multiple adn8830 devices can be either driven from a single master adn8830 device by connecting its syncout pin to each slaves syncin pin or daisy-chained by connecting each devices syncout to the next devices syncin pin. phase shifting is useful in systems that use more than one adn8830 tec controller. it ensures the adn8830 devices will not switch at the same time, which could create excessive ripple on the power supply voltage. by adjusting the phase of each device, the switching transients can be spaced equally over the clock period, reducing potential supply ripple and easing the instantaneous current demand from the supply. using a single master clock, each slave adn8830 should have a different value phase shift. for example, with four tec con- trollers, one slave device should be set for 90 of phase shift, another for 180 , and the last for 270 . in a daisy-chain configu- ration, each slave device would be set with equal phase. using the previous example, each slave would be set to 90 with its syncout pin connected to the next devices syncin pin. examples are shown in figures 7 and 8. 0.1 f 1k 1nf 24 1.5m 0.1 f 1k 1nf 24 adn8830 slave 25 29 26 28 100k 7 100k nc adn8830 master 25 29 26 r freq 28 adn8830 slave 25 29 26 1.5m 0.1 f 1k 1nf 24 28 50k 7 150k nc adn8830 slave 25 29 26 28 150k 7 50k nc 6 v dd 24 figure 7. multiple adn8830 devices driven from a master clock soft start on power-up the adn8830 can be programmed to ramp up for a specified time after the power supply is applied or after shutdown is de-asserted. this feature, known as soft start, is useful for gradually increasing the duty cycle of the pwm amplifier. the soft start time is set with a single capacitor connected from pin 27 to ground according to equation 14. ss ss c = 150 (14) where c ss is the value of the capacitor in microfarads, and ss is the soft start time in milliseconds. to set a soft start time of 15 ms, c ss should equal 0.1 f. a minimum soft start time of 10 ms is recommended to ensure proper initialization of the adn8830 on power-up. shutdown mode the adn8830 has a shutdown mode that deactivates the output stage and puts the device into a low current standby state. the current draw for the adn8830 in shutdown is less than 100 a. the shutdown input, pin 3, is active low. to shut down the device, pin 3 should be driven to logic low. once a logic high is applied, the adn8830 will reactivate after the delay set by the soft start circuitry. refer to the soft start on power-up section for more details on this feature. pin 3 should not be left floating as there are no internal pull-up or pull-down resistors. if the shutdown function is not required, pin 3 should be tied to v dd to ensure the device is always active. compensation loop the adn8830 tec controller has a built-in amplifier dedi cated for loop compensation. the exact compensation network is set by the user and can vary from a simple integrator to pi, pid, or any other type of network. the type of compensation and com- ponent values should be determined by the user since it will depend on the thermal response of the object and the tec. one method for determining these values empirically is to input a step function to tempset, thus changing the target temperature, and adjusting the compensation network to minimize the set- tling time of the objects temperature. a typical compensation network used for temperature control of a laser module is a pid loop, which consists of a very low frequency pole and two separate zeros at higher frequencies. figure 9 shows a simple network for implementing pid com- pensation. an additional pole is added at a higher frequency than the zeros to reduce the noise sensitivity of the control loop. the bode plot of the magnitude is shown in figure 10. 29 6 adn8830 master 25 nc 26 r freq adn8830 slave 25 29 26 1.5m 28 50k 7 150k 28 25 29 26 1.5m 28 50k 7 150k 25 29 26 1.5m 28 50k 7 150k nc v dd 24 24 24 24 1k 0.1 f 1nf 1k 0.1 f 1nf 1k 0.1 f 1nf adn8830 slave adn8830 slave figure 8. multiple adn8830 devices using a daisy chain d rev. C12C adn8830 the unity-gain crossover frequency of the feedforward amplifier is given as f rc tec gain db 0 1 231 80 = (15) to ensure stability, the unity-gain crossover frequency should be lower than the thermal time constant of the tec and thermistor. however, this thermal time constant may not be specified and can be difficult to characterize. there are many texts written on loop stabilization, and it is beyond the scope of this data sheet to discuss all methods and trade-offs in optimizing compensation networks. a simple method that can be used to empirically determine a pid compensation loop as shown in figure 9 involves the following procedure: 1. connect thermistor and tec to the adn8830 application circuit. power does not need to be applied to the laser diode for this procedure. monitor output voltage across the tec with an oscilloscope. 2. short c1 and open c2, leaving just r1 and r3 as a simple proportional-only compensation loop. 3. while maintaining a constant tempset voltage, increase the ratio of r1/r3, thus increasing the gain until loop oscilla- tion starts to occur. decrease this ratio by a factor of 2 from the point of oscillation. the r1/r3 ratio will likely be less than unity for most laser modules. 4. add c1 capacitor and decrease value until oscillation starts, then increase by a factor of 2. a good initial starting value for c1 is to create a unity-gain crossover of 0.1 hz based on equation 15. 5. short r2 and increase c2 until oscillation starts. at this point, either c2 can be decreased or r2 can be added to regain stability. generally speaking, r2 will be greater than r3 and c2 will be one or more orders of magnitude less than c1. 6. tempset should be adjusted with a step change while observing the output voltage settling time. a step change of 100 mv should suffice. from here, c2, r2, and even c1 can be decreased to minimize settling time at the expense of additional output voltage overshoot. 7. an additional feedback capacitor, cf, in parallel with r1 and c1, can be added to add another high frequency pole. in many cases, this improves the stability of the system without increasing the settling time as out-of-band noise is filtered out of the control signal. a 330 pf to 1 nf capacitor should suffice, if required. the typical values shown in the typical application circuit in figure 1 have r1 = 100 k , r2 = 1 m , r3 = 205 k , c1 = 10 f , c2 = 1 f, and an additional feedback capacitor of 330 pf. for most pump laser modules, this results in a 10 c tempset step settling time to within 0.1 c in less than 5 seconds. adn8830 12 compout tempctl compfb 13 r3 r2 r1 c1 14 c2 reference vo ltag e cf figure 9. implementing a pid compensation loop frequency (hz log scale) r1 r3 magnitude (log scale) r1 r2||r3 1 2 r1c1 1 2 c2(r2+r3) 1 2 r2c2 0db 1 2 r3c1 figure 10. bode plot for pid compensation using the tec controller adn8830 with a wave locker many optical applications require precision control of laser wavelength. the wavelength of the laser diode can be adjusted by changing its temperature, which is done through temperature control of the tec. wavelength control can be done by feeding a wave locker or etalon output back to the microprocessor and using the microprocessor to calculate and reinstruct the tec controller with a new target temperature. however, this method is computationally expensive and has time delays before the adjustment is done. a faster responding and simpler method is to feed the wave locker signal back to the tec controller for direct temperature control. the adn8830 is designed to be compatible with a wave locker controller. figure 11 shows the basic schematic. the te mpctl output from adn8830 is proportional to the objects actual temperature. this voltage is fed to the wave locker controller. also fed to the wave locker controller are the photodiode out- puts from the wave locker, as well as the laser diode power and a digital signal indicating a functional laser diode, both of which come from the cw controller. the output of the wave locker controller is then connected to the input of the compensation network. this allows the wave locker controller to adjust the tec temperature based on the current temperature of the object, the current wavelength of the laser diode, and the target wavelength. once the target wavelength is reached, the wave locker controller sends a signal to the microcontroller indicating that the laser signal is good. adn8830 compout 14 compfb 13 compensation network tempctl 12 temp in locker pd1 locker pd2 laser diode power laser diode good from locker from cw controller wave locker good to micro- processor tec control figure 11. using the adn8830 with a wave locker d rev. adn8830 C13C using tempout to measure temperature the tempout pin is a voltage that is proportional to the difference between the target temperature and the measured thermistor temperature. the full equation for the voltage at tempout is tempout thermin tempset =+ () 15 3 .C (16) the voltage range of tempout is 0 v to 3.0 v and is inde- pendent of power supply voltage. setting the maximum tec voltage and current the adn8830 can be programmed for a maximum output volt- age to protect the tec. a voltage from 0 v to 1.5 v applied to the vlim (pin 15) input to the adn8830 sets the maximum tec voltage, v tec, max . this voltage can be set with either a resistor divider or from a dac. because the output of the adn8830 is bidirectional, this voltage sets both the upper and lower limits of the tec voltage. the equation governing v tec, max is given in equation 17 and the graph of this equation is shown in figure 12. v v vlim tec max , .C = () 15 4 (17) vlim (v) 5 0 0 2.0 0.5 v tec, max (v) 1.0 1.5 4 3 2 1 figure 12. vlim voltage vs. maximum tec voltage if the supply voltage is lower than v tec, max , the maximum tec voltage will obviously be equal to the supply voltage. the voltage to vlim should not exceed 1.5 v since this causes improper opera tion of the output voltage limiting circuitry. setting vlim to 1.5 v can be used to deactivate the tec current without shutting down the adn8830 in the event of a system failure. if a maximum tec voltage is not required, vlim should be con- nected to ground. it is not advisable to leave vlim floating as this would cause unpredictable output behavior. this feature should be used to limit the maximum output current to the tec as specified in the tec data sheet. for example, if the maximum tec voltage is specified at 2 v, vlim should be set to 1 v. the maximum output voltage is then set to 2v. output driver amplifiers the output voltage across the tec as measured from pin 19 to pin 9 can be monitored at pin 16. this is labeled as vtec in the typical application schematic in figure 1. the voltage at vtec can vary from 0 v to 3 v independent of the power supply voltage. its equation is given as vtec v v out a out b = () + 025 15 .C. (18) where v out a and v out b are the voltages at pins 19 and 9, respec- tively. the ripple voltage at pin 19 is filtered out internally and does not appear at vtec, leaving it as an accurate dc output of the tec voltage. the tec is driven with a differential voltage, allowing current to flow in either direction through the tec. this can provide heat transfer either to or from the object being regulated without the use of a negative voltage rail. the maximum output voltage across the tec is set by the voltage at vlim (pin 15). refer to the setting the maximum tec voltage and current section for details on this operation. with vlim set to ground, the maximum output voltage is the power supply voltage, v dd . to achieve a differential output, the adn8830 has two separate output stages. out a is a switched output or pulse-width modulated (pwm) amplifier, and out b is a high gain linear amplifier. although they achieve the same result, to provide constant voltage and high current, their operation is different. the exact equations for the two outputs are out a compout out b = () + 415 C. (19) out b compout = () + CC.. 14 1 5 1 5 (20) where compout is the voltage at pin 13. the voltage at compout is determined by the compensation network that is fed by the input amplifier, which receives its input voltage from tempset and thermin. equation 20 is valid only in the linear region of the linear amplifier. out b has a lower limit of 0 v and an upper limit of the power supply. because the compout voltage is not readily known, equa- tion 20 can be rewritten in terms of the tec voltage, vtec, which is defined as out b C out a. out b vtec = + 415 . (21) in figure 1, pins 10 and 11 provide the gate drive for q3 and q4, which complete the linear output amplifier. this output voltage is fed back to pin 9 (out b) to close its loop. the gate-to-drain capacitance of q3 and q4 provide the com pensation for the linear amplifier. if using the recommended fdw2520c transistors, it will be necessary to add an additional 2.2 nf of capacitance from the gate to the drain of the pmos transistor to maintain stability. a 3.3 nf capacitor should also be connected from the drain to ground to prevent small oscillations when there is very little or no current through the tec. these extra capacitors are specified only when using fdw2520c transistors in the linear amplifier. if other transistors are used, these values may need to be adjusted. to ensure the linear amplifier is stable, the total gate-to-source capacitance for both q3 and q4 should be at least 2.5 nf. refer to the transistors data sheet for its typical gate-to-drain capacitance values. the output of the linear amplifier is proportional to the voltage at pin 13 (compout). because the linear amplifier operates with a gain of 14, its output will typically be at either ground or v dd if there is more than about 100 ma of current flowing through the tec. this ensures q3 and q4 will not be a domi- nant source of power dissipation at high output currents. d rev. C14C adn8830 inductor select i on in add i t i on to the external trans i stors, the pwm ampl i f i er requ i res an i nductor and a capac i tor at i ts output to f i lter the sw i tched output waveform . proper i nductor select i on i s i mportant to ach i eve the best eff i c i ency . the duty cycle of the pwm sets the out a output voltage and i s d out a v dd = (22) the average current through the i nductor i s equal to the tec current . the r i pple current through the i nductor, i l , var i es w i th the duty cycle and i s equal to i vd d lf l dd clk = () 1C (23) where f clk i s the clock frequency as set by the res i stor r freq at p i n 26 or an external clock frequency . refer to the sett i ng the sw i tch i ng frequency sect i on for more i nformat i on . select i ng a faster sw i tch i ng frequency or a larger value i nductor w i ll reduce the r i pple current through the i nductor . the waveform of the i nductor current i s shown i n f i gure 13 . time i tec inductor current (a) i l 1 f clk t = figure 13. current waveform through inductor it i s i mportant to select an i nductor that can tolerate the max i - mum poss i ble current that could pass through i t . most tecs are spec i f i ed w i th a max i mum voltage and current for proper and rel i able operat i on . the max i mum i nstantaneous i nductor current can be found as ii i l max tec max l ,, . =+ 05 (24) where i l can be found from equat i on 23 w i th the appropr i ate duty cycle calculated from equat i on 22 w i th out a = v tec, max . des i gn example 3 a tec i s spec i f i ed w i th a max i mum current of 1 . 5 a and max i - mum voltage of 2 . 5 v . the adn8830 w i ll be operat i ng from a 3 . 3 v supply voltage w i th a 200 khz clock and a 4 . 7 h i nductor . the duty cycle of the pwm ampl i f i er at 2 . 5 v i s calculated to be 75 . 8% . us i ng equat i on 23, the i nductor r i pple current i s found to be 664 ma . from equat i on 24, the max i mum i nduc tor current w i ll be 1 . 82 a and should be cons i dered when select i ng the i nductor . not i ce that i ncreas i ng the clock frequency to 1 mhz would reduce i l, max to 1 . 56 a . des i gn example 4 us i ng the same tec as above, the adn8830 w i ll be powered from 5 . 0 v i nstead . here, the duty cycle i s 50%, wh i ch happens to be the worst-case duty cycle for i nductor current r i pple . now dil equals 1 . 33 a w i th a 200 khz clock, and i l, max i s 2 . 83 a . reduc i ng the i nductor r i pple current i s another compell i ng reason to operate the adn8830 from a 3 . 3 v supply i nstead . table ii l i sts some i nductor manufacturers and part numbers along w i th some key spec i f i cat i ons . the column i max refers to the max i mum current at wh i ch the i nductor i s rated to rema i n l i near . although h i gher currents can be pushed through the i nductor, eff i c i ency and r i pple voltage w i ll be dramat i cally degraded . th i s i s by no means a complete l i st of manufacturers or i nductors that can be used i n the appl i cat i on . more i nformat i on on these i nductors i s ava i lable at the i r webs i tes . note the trade-offs between i nductor he i ght, max i mum current, and ser i es res i stance . smaller i nductors cannot handle as muh current and therefore requ i re h i gher clock speeds to reduce the i r r i pple current . they also have h i gher ser i es res i stance, wh i ch can lower the overall eff i c i ency of the adn8830 . pwm output f i lter requ i rements the sw i tch i ng of q1 and q2 creates a pulse w i dth modulated (pwm) square wave from 0 v to v dd . th i s square wave must be f i ltered suff i c i ently to create a steady voltage that w i ll dr i ve the tec . the r i pple voltage across the tec i s a funct i on of the i nductor r i pple current, the l-c f i lter cutoff frequency, and the equ i valent ser i es res i stance (esr) of the f i lter capac i tor . the equ i valent c i rcu i t for the pwm s i de i s g i ven i n f i gure 14 . table ii . part i al l i st of inductors and key spec i f i cat i ons inductance ( h) i max (a) r s, typ (m )he i ght (mm) part number manufacturer webs i te 4 . 71 . 1 200 1 lpo1704-472m co i lcraft www . co i lcraft . com 4 . 71 . 59 55 2 a918cy-4r7m toko www . toko . com 4 . 73 . 948 2 . 8 up2 . 8b-4r7 cooper www . cooperet . com 4 . 71 . 5 90 3 do1608c-472 co i lcraft www . co i lcraft . com 4 . 71 . 32 56 3 cdrh4d28 4r7 sum i da www . sum i da . com 4 . 77 . 512 4 . 5 892nas-4r7m toko www . toko . com 4 . 7 * 5 . 418 5 . 2 do3316p-472 co i lcraft www . co i lcraft . com 10 2 . 780 2 . 8 up2 . 8b-100 cooper www . cooperet . com 15 8 32 8 do5022p-153hc co i lcraft www . co i lcraft . com 47 4 . 586 7 . 1 do5022p-473 co i lcraft www . co i lcraft . com * recommend i nductor i n typ i cal appl i cat i on c i rcu i t f i gure 1 . d rev. adn8830 C15C out b c1 r1 r l l1 r2 pvdd p1 q1 n1 q2 out a v x denotes pgnd figure 14. equivalent circuit for pwm amplifier and filter in this circuit, r l is the tec resistance, r2 is the parasitic resistance of the inductor combined with the equivalent r ds, on of q1 and q2, and r1 is the esr of c1. the voltage, v x , is the pulse-width modulated waveform that switches between pvdd and ground. this is a second-order low-pass filter with an exact cutoff frequency of f rr rrcl c l l = + + () 1 2 2 111 (25) practically speaking, r1 and r2 are several tens of milliohms and are much smaller than the tec resistance, which can be a few ohms. the cutoff frequency can be roughly approximated as f cl c = 1 2 1 11 (26) this cutoff frequency should be much lower than the clock frequency to achieve adequate filtering of the switched output waveform. also of importance is the damping factor, , of the l-c filter. too low a damping factor will result in a longer settling time and could potentially cause stability problems for the temperature control loop. neglecting r1 and r2 again, the damping factor is simply = 1 2 1 1 r l c l (27) using the recommended values of l1 = 4.7 h and c1 = 22 f results in a cutoff frequency of 15.7 khz. with a tec resistance of 2 , the damping factor is 0.12. the cutoff frequency can be decreased to lower the output voltage ripple with slower clock frequencies by increasing l1 or c1. increasing c1 may appear to be a simpler approach as it would not increase the physical size of the inductor, but there is a potential stability danger in lowering the damping factor too far. it is recommended that remain greater than 0.05 to provide a reasonable settling time for the tec. increasing also makes finding the proper pid compensation easier as there is less ringing in the l-c output filter. to allow adequate phase and gain margin for the pwm amplifier, table iii should be used to find the lower limit of cutoff frequency for a given damping factor. table iii. minimum l-c filter cutoff frequency vs. damping factor f c, min (khz) 0.05 8 0.1 4 0.2 2 0.3 1.9 0.5 1.6 > 0.707 1.5 calculating pwm output ripple voltage although it may seem that f c can be arbitrarily lowered to re duce output ripple, the ripple voltage is also dependent on the esr of c1, shown as r1 in figure 14. this resistance creates a zero that turns the second-order filter into a first-order filter at high frequencies. the location of this zero is z rc 1 1 211 = (28) with a clock frequency greater than z1, and presumably greater than f c , the output voltage ripple is ? out a i r l = 1 (29) out a vd dr lf for f z dd clk clk = () > () 11 1 1 C (30) the worst-case voltage ripple occurs when the duty cycle of the pwm output is exactly 50%, or when out a = 0.5 v dd . as shown in equation 31 out a vr fl for f z max dd clk clk > () 1 41 1 (31) here it can be directly seen that increasing the inductor value or clock frequency will reduce the ripple. choosing a low esr capacitor will ensure r1 remains low. operating from a lower supply voltage will also help reduce the output ripple voltage from the l-c filter. with a clock frequency equal to z 1 but presumably greater than f c , the worst-case output voltage ripple is out a v rc f lc f for f z max dd clk clk clk = + () = () 16 1 1 1 32 1 1 1 22 2 (32) which, if f clk < z 1, can be further simplified to out a v lc f for f z max dd clk clk =< () 32 1 1 1 2 (33) a typical 100 f surface-mount electrolytic capacitor can have an esr of over 100 m , pulling this zero to below 16 khz, and resulting in an excess of ripple voltage across the tec. low esr capacitors, such as ceramic or polymer aluminum capacitors, are recommended instead. polymer aluminum capacitors can provide more bulk capacitance per unit area over ceramic ones, saving board space. table iv shows a limited list of capacitors with their equivalent series resistances. this is by no means a complete list of all capacitor manufacturers or capacitor types that can be used in the application. the 22 f capacitor recommended has a maximum esr of 35 m , which puts z1 at 207 khz. using a 3.3 v supply with the recommended inductor and capacitor listed with a 1 mhz clock frequency will yield a worst-case ripple voltage at out a of about 6 mv. external fet requirements external fets are required for both the pwm and linear amplifiers that drive out a and out b from the adn8830. although it is important to select fets that can supply the maximum current required to the tec, they should also have a low enough resis- tance (r ds, on ) to prevent excessive power dissipation and improve efficiency. other key requirements from these fet pairs are slightly different for the pwm and linear outputs. d rev. C16C adn8830 the gate drive outputs for the pwm amplifier at p1 (pin 21) and n1 (pin 22) have a typical nonoverlap delay of 65 ns. this is done to ensure that one fet is completely off before the other fet is turned on, preventing current from shooting through both simultaneously. the input capacitance (c iss ) of the fet should not exceed 5 nf. the p1 and n1 outputs from the adn8830 have a typi cal output impedance of 6 . this creates a time constant in combination with c iss of the external fets equal to 6 c iss . to ensure shoot-through does not occur through these fets, this time constant should remain less than 30 ns. the linear output from the adn8830 uses n2 (pin 10) and p2 (pin 11) to drive the gates of the linear side fets, shown as q3 and q4 in figure 1. local compensation for the linear am pli- fier is achieved through the gate-to-drain capacitances (c gd ) of q3 and q4. the value of c gd , which can be determined from the data sheet, is usually referred to as c rss , the reverse transfer capacitance. the exact c rss value should be determ ined from a graph that shows capacitance versus drain-to-source voltage, using the power supply voltage as the appropriate v ds . to ensure stability of the linear amplifier, the total c gd of the pmos device, q3, should be greater than 2.5 nf and the total c gd of the nmos should be greater than 150 pf. external capacitance can be added around the fet to increase the effec tive c gd of the transistor. this is the function of c6 in the typical application schematic shown in figure 1. if external capaci tance must be added, it will generally only be required around the pmos transistor. in the event of zero output current through the tec, there will be no current flowing through q3 and q4. in this condition, these fets will not provide any small signal gain and thus no negative feedback for the linear amplifier. this leaves only a feedforward signal path through c gd , which could cause a settling problem at out b. this is often seen as a small signal oscillation at out b, but only when the tec is at or very near zero current. the remedy for this potential minor instability is to add capacitance from out b to ground. this may need to be d eter- mined empirically, but a good starting point is 1.5 times the total c gd . this is the function of c12 in figure 1. note that while adding more c gd around q3 and q4 will help to ensure stability, it could potentially increase instability in the zero cur rent dead band region, requiring additional capacitance from out b to ground. bear in mind that the addition of these capacitors is only for local stabilization. the stability of the entire tec appli- cation may need adjustment, which should be done around the compensa tion amp lifier. this is covered in the compensation loop section. there is one additional consideration for selecting both the linear output fets; they must have a minimum threshold voltage (v t ) of 0.6 v. lower threshold voltages could cause shoot-through current in the linear output transistors. table v shows the recommended fets that can be used for the linear output in the adn8830 application. table v includes the appropriate external gate-to-drain capacitance (external c gd ) and snubber capacitor value (c snub ) connected from out b to ground that should be added to ensure local stability. table vi shows the recommended pwm output fets. al though other transistors can be used, these combinations have been tested and are proved stable and reliable for typical applications. data sheets for these devices can be found at their respective websites: fairchild C www.fairchildsemi.com vishay siliconix C www.vishay.com international rectifier C www.irf.com calculating power dissipation and efficiency the total efficiency of the adn8830 application circuit is simply the ratio of the output power to the tec divided by the total power delivered from the supply. the idea in minimizing power dissipation is to avoid both drawing additional power and reduc- ing heat generated from the circuit. the dominant sources of power dissipation will include resistive losses, gate charge loss, core loss from the inductor, and the current used by the adn8830 itself. the on-channel resistance of both the linear and pwm output fets will affect efficiency primarily at high output currents. because the linear amplifier operates in a high gain configura tion, it will be at either ground or v dd when significant current is flowing through the tec. in this condition, the power dissipa tion through the linear output fet will be pri fet lin ds on tec ,, = 2 (34) using either the r ds, on for the nmos or the pmos depending on the direction of the current flow. in the typical application setup in figure 2, if the tec is cooling the target object, the pmos is sourcing the current. if the tec is heating the object, the nmos will be sinking current. table iv. partial list of capacitors and key specifications value ( f) esr (m ) voltage rating (v) part number manufacturer website 10 60 6.3 nsp100m6.3d2tr nic components www.niccomp.com 22 * 35 8 esrd220m08b cornell dubilier www.cornell-dubilier.com 22 35 8 nsp220m8d5tr nic components www.niccomp.com 22 35 8 EEFFD0K220R panasonic www.maco.panasonic.co.jp 47 25 6.3 nsp470m6.3d2tr nic components www.niccomp.com 68 18 8 esrd680m08b cornell dubilier www.cornell-dubilier.com 100 95 10 594d107x_010c2t vishay www.vishay.com * recommend capacitor in typical application circuit figure 1. d rev. adn8830 C17C although the fets that drive out a alternate between q1 and q2 being on, they have an equivalent series resistance that is equal to a weighted average of their r ds, on values. rdr dr eqiv ds p ds n = + () ,, C 11 1 (35) the resistive power loss from the pwm transistors is then pri fet pwm eqiv tec , = 2 (36) there is also a power loss from the continuing charging and discharging of the gate capacitances on q1 and q2. the power dissipated due to gate charge loss ( p gcl ) is pcvf gcl iss dd clk = 1 2 2 (37) using the appropriate input capacitance ( c iss ) for the nmos and pmos. both transistors are switching, so p gcl should be calculated for each one and will be added to find the total power dissipated from the circuit. the series resistance of the inductor, r 2 from figure 14, will also exhibit a power dissipation equal to pri r tec 2 2 2 = (38) core loss from the inductor arises as a result of nonidealities of the inductor. although this is difficult to calculate explicitly, it can be estimated as 80% of p rls at 1 mhz switching frequen- cies and 50% of p rl at 100 khz. judging conservatively pp loss rl = 08 . (39) finally, the power dissipated by the adn8830 is equal to the current used by the device multiplied by the supply voltage. again, this exact equation is difficult to determine as we have already taken into account some of the current while finding the gate charge loss. a reasonable estimate is to use 40 ma as the total current used by the adn8830. the power dissipated from the device itself is pvma adn dd 8830 10 = (40) there are certainly other minor mechanisms for power dissipa- tion in the circuit. however, a rough estimate of the total power dissipated can be found by summing the preceding power dissi- pation equations. efficiency is then found by comparing the power dissipated with the required output power to the load. efficiency p pp load load diss tot = + , (41) where piv load load load = the measured efficiency of the system will likely be less than the calculated efficiency. measuring the efficiency of the application circuit is fairly simple but must be done in an exact manner to ensure the correct numbers are being measured. using two high current, low impedance ammeters and two voltmeters, the cir- cuit should be set up as shown in figure 15. a v dd power supply gnd adn8830 v v a tec load figure 15. measuring efficiency of the adn8830 circuit table v. recommended fets for linear output amplifier part number type c gd (nf) ext. c gd (nf) c snub (nf) r ds, on (m )i max (a) manufacturer fdw2520c * nmos 0.17 18 6.0 fairchild pmos 0.15 2.2 3.3 35 4.5 fairchild irf7401 nmos 0.5 22 8.7 international rectifier irf7233 pmos 2.2 1.0 3.3 20 9.5 international rectifier fdr6674a nmos 0.23 9.5 11.5 fairchild fdr840p pmos 0.6 1.0 3.3 12 10 fairchild * recommend transistors in typical application circuit figure 1. table vi. recommended fets for pwm output amplifier part number type c iss (nf) r ds,on (m ) continuous i max (a) manufacturer fdw2520c * nmos 1.33 18 6.0 fairchild pmos 1.33 35 4.5 fairchild si7904dn nmos 1.0 30 5.3 vishay siliconix si7401dn pmos 3.5 17 7.3 vishay siliconix irf7401 nmos 1.6 22 8.7 international rectifier irf7404 pmos 1.5 40 6.7 international rectifier * recommend transistors in typical application circuit figure 1. d rev. C18C adn8830 the voltmeter to the tec or output load should include the series ammeter since the power delivered to the ammeter is considered part of the total output power. however, the voltmeter measuring the voltage delivered to the adn8830 circuit should not include the series ammeter from the power supply. this prevents a false supply voltage power measurement since we are interested only in the supply voltage power delivered to the adn8830 circuit. figures 16 and 17 show some efficiency measurements using the typical appli- cation circuit shown in figure 1. i tec (ma) 100 80 0 0 2,000 500 efficiency (%) 1,000 1,500 60 40 20 v sy = 5v v sy = 3v figure 16. efficiency with f clk = 1 mhz i tec (ma) 100 80 0 0 2,000 500 efficiency (%) 1,000 1,500 60 40 20 v sy = 5v v sy = 3v figure 17. efficiency with f clk = 200 khz note that higher efficiency can be achieved using a lower supply voltage or a slower clock frequency. this is due to the fact that the dominant source of power dissipation at high clock frequencies is the gate charge loss on the pwm transistors. layout considerations the two key considerations for laying out the board for the adn8830 are to minimize both the series resistance in the output and the potential noise pickup in the precision input section. the best way to accomplish both of these objectives is to divide the layout into two sections, one for the output components and the other for the remainder of the circuit. these sections should have independent power supply and ground current paths that are each connected together at a single point near the power supply. this is used to minimize power supply and ground voltage bounce on the more sensitive input stages to the adn8830 caused by the switch- ing of the pwm output. such a layout technique is referred to as a star ground and supply connection. figure 18 shows a block dia- gram of the concept. v dd power supply gnd tec or load output section noise sensitive section pgnd pvdd agnd avdd figure 18. using star connections to minimize noise pickup from switched output the low noise power and ground are referred to as avdd and agnd, with the output supply and ground paths labeled pvdd and pgnd. these pins are labeled on the adn8830 and should be connected appropriately. both sets of external fets should be connected to pvdd and pgnd. all output filtering and pvdd supply bypass capacitors should be connected to pgnd. all remaining connections to ground and power supply should be done through avdd and agnd. a 4-layer board layout is rec- ommended for best performance with split power and ground planes between the top and bottom layers. this provides the lowest impedance for both supply and ground points. setting the adn8830 above the agnd plane will reduce the potential noise injection into the device. figure 19 shows the top layer of the layout used for the adn8830 evaluation boards, highlighting the power and ground split planes. figure 19. top layer reference layout for adn8830 proper supply voltage bypassing should also be taken into consid- eration to minimize the ripple voltage on the power supply. a minimum bypass capacitance of 10 f should be placed in close proximity to each component connected to the power supply. this includes pins 8 and 20 on the adn8830 and both external pmos transistors. an additional 0.1 f capacitor should be placed in parallel to each 10 f capacitor to provide bypass for high fre- quency noise. using a large bulk capacitor, 100 f or greater, in parallel with a low esr capacitor where avdd and pvdd con- nect will further improve voltage supply ripple. this is covered in more detail in the power supply ripple section. d rev. adn8830 C19C power supply ripple minimizing ripple on the power supply voltage can be an impor- tant consideration, particularly in signal source laser applications. if the laser diode is operated from the same supply rail as the tec controller, ripple on the supply voltage could cause inadvertent modulation of the laser frequency. as most laser diodes are driven from a 5 v supply, it is recommended the adn8830 be operated from a separate 3.3 v regulated supply unless higher tec voltages are required. operation from 3.3 v also improves efficiency, thus minimizing power dissipation. the power supply ripple is primarily a function of the supply by- pass capacitance, also called bulk capacitance, and the inductor ripple current. similar to the l-c filter at the pwm amplifier output, using more capacitance with low equivalent series resis- tance (esr) will lower the supply ripple. a larger inductor value will reduce the inductor ripple current, but this may not be practical in the application. a recommended approach is to use a standard electrolytic capacitor in parallel with a low esr capacitor. a surface-mount 220 f electrolytic in parallel with a 22 f poly- mer aluminum low esr capacitor can occupy an approximate total board area of only 0.94 square inches or 61 square millimeters. using these capacitors along with a 4.7 h inductor can yield a supply ripple of less than 5 mv. high frequency transient spikes may appear on the supply voltage as well. this is due to the fast switching times on the pwm transis- tors and the sharp edges of their gate voltages. although these transient spikes can reach several tens of millivolts at their peak, they typically last for less than 20 ns and have a resonance greater than 100 mhz. additional bulk capacitance will not appreciably affect the level of these spikes as such capacitance is not reactive at these frequencies. adding 0.01 f ceramic capacitors on the sup- ply line near the pwm pmos transistor can reduce this switching noise. inserting an rf inductor with a high-q around 100 mhz in series with pvdd will also block this noise from traveling back to the power supply. setting maximum output current and short-circuit protection although the maximum output voltage can be programmed through vlim to protect the tec from overvoltage damage, the user may wish to protect the adn8830 circuit from a possible short circuit at the output. such a short could quickly damage the external fets or even the power supply since they would attempt to drive excessive current. figure 20 shows a simple modification that will protect the system from an output short circuit. sd c1 1 f r2 1k denotes pgnd r1 1m d1 ma116ct-nd or equivalent avdd q1 fdv304p or equivalent pvdd r s 10m r4 100k r3 1k pvdd denotes agnd to fets and decoupling caps v s v x ad8601 figure 20. implementing output short-circuit protection a 10 m resistor placed in series with the pvdd supply line creates a voltage drop proportional to the absolute value of the output current. the ad8601 is a cmos amplifier that is configured as a com- parator. as long as the voltage at its inverting input (v s ) exceeds the voltage set by the resistor divider at the noninverting input (v x ), the gate of q1 will remain at ground. this leaves q1 on, effectively connecting d1 to the positive rail and leaving the voltage on c1 at v dd . should enough current flow through r s to drop v s below v x , q1 will turn off and c1 will discharge through r2 down to a logic low to activate the adn8830 shutdown. once v s returns to a voltage greater than v x , q1 will turn back on and c1 will charge back to v dd through r1. the shutdown and reactivation time constants are approximately sd on cr cr = = 11 11 (42) the shutdown time constant should be a minimum of 10 clock cycles to ensure high current switching transients do not trigger a false activation. if powered from 5 v, the circuit shown will shut down the adn8830 should pvdd deliver over 5 a for more than 1 ms. after shutdown, the circuit will reactivate the adn8830 in about 1 second. the voltage drop across r s is found as v irr v r out l s dd s = 2 (43) where r l is the load resistance or resistance of the tec and is the efficiency of the system. an estimate of efficiency can be calculated either from the calculating power dissipation and efficiency section or from figures 16 and 17. a reasonable approximation is = 0.85. although the exact resistance of a tec varies with tempera- ture, an estimation can be made by dividing the maximum voltage rating of the tec by its maximum current rating. in addition to providing protection against a short at the output, this circuit will also protect the fets against shoot-through current. shoot-through will not occur when using the recommended transistors and additional capacitance shown in tables v and vi. however, if different transistors are used where their shoot- through potential is unknown, implementing the short-circuit protection circuit will unconditionally protect these transistors. to set a maximum output current limit, use the circuit in figure 21. this circuit can share the 10 m power supply shunt resistor as the short-circuit protection circuit to sense the output current. in normal operation q1 is on, pulling the adn8830 vlim pin down to the voltage set by vlimit. this sets the maximum out- put voltage limit as described in the setting the maximum tec voltage and current section. to vlim r2 1.47k denotes pgnd avdd q1 fdv301n or equivalent pvdd r s 10m r4 100k r3 178 pvdd denotes agnd v sy v x ad8605 vlimit (0v to 1.5v) r1 3.48k c1 1nf to fets and decoupling caps figure 21. setting a maximum output current limit d rev. C20C adn8830 if the voltage at v sy drops below v x , q1 is turned off and the vlim pin will be set to 1.5 v, effectively setting the maximum voltage across the outputs to 0 v. the voltage divider for v x is calculated from equation 43. design example 5 a maximum output current limit needs to be set at 1.5 a for a tec with a maximum voltage rating of 2.5 v. the adn8830 is powered from 5 v. the tec resistance is estimated at 1.67 and efficiency at 85%. using equation 43, the voltage drop across r s will be 8.8 mv when 1.5 a is delivered to the tec. the trip voltage v x is set to 4.991 v with r3 = 178 and r4 = 100 k as shown in figure 21. to set the output voltage limit to 2.5 v, the voltage at vlimit should be set to 0.875 v according to equation 17. the c1 capacitor is added to smooth the voltage transitions at vlim. once an overcurrent condition is detected, the output voltage will turn down to 0 v within 30 ms. for a more exact measurement of the output current, place a sense resistor in series with the output load, as shown in figure 23. the ad626 instrumentation amplifier is set for a gain of 100 with a reference voltage of 2.47 v from vref. the output of the ad626 is equal to 100 r s i l and is fed to the ad8602, which is set up as a window comparator. with v x greater than vlo but less than vhi, vlim will be pulled down to the volt- age at vlimit. should v x fall outside the voltage window, vlim will be pulled to 1.5 v as in figure 21. the trip points should be set according to vhi vref r i vlo vref r i s limit s limit =+ = + 100 100 C C (44) avdd q1,q2 fdg6303n or equiva- lent 8 to vref 1nf avdd to out b r s 10m i l to tec vlimit (0v to 1.5v) to vlim r2 1.47k r1 3.48k avdd 200k 300k 300k 200k v x v lo ad8602 ad626 avdd v hi figure 23. high accuracy output current limit the upper and lower trip point voltages can be set indepen dently, allowing different maximum output current limits depending on the direction of the current. the resistor divider for vhi and vlo is tapped to vref to maintain window accuracy with any changes in vref. using the values from figure 23 with a 5 v supply, the output current will not exceed 1.5 a in either direction. adding the current sensing resistor will slightly reduce effi ciency. the power dissipated by this resistor is d itec2 r s if the tec is heating, or (1Cd) itec2 r s if the tec is cooling. include this when calculating efficiency as described in the calculating power dissipation and efficiency section. 25mv/ c out oa adt70 1k out ia Cin oa 5.11k agnd 4.99k rga rgb inst amp Cin ia +in ia +in oa r3 1k r3 82.5 i outb i outa rtd 1k r3 82.5 gnd sense 5v note: additional pins omitted for clarity to therm_in = 1v @ 25 c figure 22. using an rtd for temperature feedback to the adn8830 d rev. adn8830 C21C using an rtd for temperature sensing the adn8830 can be used with a resistive temperature device (rtd) as the temperature feedback sensor. the resistance of an rtd is linear with respect to temperature, offering an advan- tage over thermistors that have an exponential relationship to temperature. a constant current applied through an rtd will yield a voltage proportional to temperature. however, this volt- age could be on the order of only 0.5 mv/ c, thus requiring the use of additional amplification to achieve a usable signal level. the adt70 from analog devices can be used to bias and am plify the voltage across an rtd, which can then be fed directly to the thermin pin on the adn8830 to provide temperature feedback for the tec controller. the adt70 uses a 0.9 ma current source to drive the rtd and an instrumentation ampli- fier with adjustable gain to boost the rtd voltage. application notes and typical schematics for this device can be found in the adt70 data sheet. most rtds have a positive temperature coefficient, also called tempco, as opposed to thermistors, which have a negative tem pco. for the out a output to drive the tecC input as shown in figure 1, the signal from an rtd must be conditioned to create a negative tempco. this can be easily done using an inverting amplifier. alternately, out a can be connected to drive tec+ with out b driving tecC with a positive tempco at thermin. this is highlighted in the output driver amplifiers section. for the adn8830, proper operation care should be taken to ensure the voltage at thermin remains within 0.4 v and 2.0 v. using a 1 k rtd with the adt70 will yield a thermin voltage of 0.9 v at 25 c. using the application circuit shown in figure 22 will provide a nominal output voltage of 1.0 v at 25 c and a total gain of 66.7 mv/ . using an rtd with a temperature coefficient of 0.375 / c will give a thermin voltage swing from 1.5 v at 5 c to 0.5 v at 45 c, well within the input range of the adn8830. using a resistive load as a heating element the adn8830 can be used in applications that do not neces- sarily drive a tec but require only a high current output into a load resistance. such applications generally only require heating above ambient temperature and simply use the power dissipated by the load element to accomplish this. because the power dissipated by such an element is proportional to the square of the output voltage, the adn8830 application circuit must be modified. figure 24 shows the preferred method for driving a heating element load. out b c1 r l l1 pvdd p1 q1 n1 q2 n2 q3 out a no connection to p2 required figure 24. using the adn8830 to drive a heating element current is delivered from the pwm amplifier through q3 when the voltage at thermin is lower than tempset. if the object temperature is greater than the target temperature, q3 will turn off and the current through the load goes to zero, allowing the object to cool back toward the ambient temperature. as the target temperature is approached, a steady output current should be reached. naturally, a proper compensation network must be found to ensure stability and adequate temperature settling time. the p2 output from the adn8830 should be left unconnected. suggested pad layout for cp-32 package figure 25 shows the dimensions for the pc board pad layout for the adn8830, which is a 5 5, 32-lead lead frame chipscale pack age. this package has a metallic heat slug that should be soldered to a copper pad on the pc board. although the pack- age slug is electrically connected to the substrate of the ic, the copper pad should be left electrically floating. this prevents potential noise injection into the substrate while maintaining good thermal conduction to the pc board. 0.10 (0.0039) 3.78 (0.1488) 5.36 (0.2110) 3.68 (0.1449) 0.28 (0.0110) 0.50 (0.0197) 0.69 (0.0272) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design thermal pad should be soldered to an electrically floating pad on the pc board package outline figure 25. suggested pc board layout for cp-32 pad landing d adn8830 C22C rev. d outline dimensions figure 26. 32-lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp-32-7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adn8830acpz ?40c to +85c 32-lead lead frame chip scale package [lfcsp_wq] cp-32-7 adn8830acpz-reel ?40c to +85c 32-lead lead frame chip scale package [lfcsp_wq] cp-32-7 adn8830acpz-reel7 ?40c to +85c 32-lead lead frame chip scale package [lfcsp_wq] cp-32-7 1 z = rohs compliant part. revision history 3/12rev. c to rev. d added epad notation ..................................................................... 3 updated outline dimensions ........................................................ 22 changes to ordering guide ........................................................... 22 11/03rev. b to rev. c changes to ordering guide ............................................................. 3 deleted figure 24 ............................................................................ 21 deleted boosting the output voltage section ............................. 22 deleted figure 26 ............................................................................ 22 deleted equations 45, 46 and 47 ................................................... 22 updated outline dimensions ........................................................ 23 8/03rev. a to rev. b updated ordering guide ................................................................. 3 updated thermal setup section ..................................................... 8 updated outline dimensions ........................................................ 23 2/03rev. 0 to rev. a renumbered figures .......................................................... universal changes to thermistor setup section ............................................ 8 changes to figure 14 ...................................................................... 15 changes to figure 23 ...................................................................... 20 changes to figure 25 ...................................................................... 21 updated outline dimensions ........................................................ 23 compliant to jedec standards mo-220-whhd. 112408-a 1 0.50 bsc bottom view top view pin 1 indicator 32 9 16 17 24 25 8 exposed pad p i n 1 i n d i c a t o r 3.25 3.10 sq 2.95 s eating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min ?2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d02793-0-3/12(b) |
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